W25Q64BV
11.2.14
Octal Word Read Quad I/O (E3h)
The Octal Word Read Quad I/O (E3h) instruction is similar to the Fast Read Quad I/O (EBh) instruction
except that the lower four Address bits (A0, A1, A2, A3) must equal 0. As a result, the four dummy clocks
are not required, which further reduces the instruction overhead allowing even faster random access for
code execution (XIP). The Quad Enable bit (QE) of Status Register-2 must be set to enable the Octal
Word Read Quad I/O Instruction. To ensure optimum performance the High Performance Mode
(HPM)instruction (A3h) must be executed once, prior to the Octal Word Read Quad I/O Instruction.
Octal Word Read Quad I/O with “Continuous Read Mode”
The Octal Word Read Quad I/O instruction can further reduce instruction overhead through setting the
“Continuous Read Mode” bits (M7-0) after the input Address bits (A23-0), as shown in figure 14a. The
upper nibble of the (M7-4) controls the length of the next Octal Word Read Quad I/O instruction through
the inclusion or exclusion of the first byte instruction code. The lower nibble bits of the (M3-0) are don’t
care (“x”). However, the IO pins should be high-impedance prior to the falling edge of the first data out
clock.
If the “Continuous Read Mode” bits (M7-0) equals “Ax” hex, then the next Octal Word Read Quad I/O
instruction (after /CS is raised and then lowered) does not require the E3h instruction code, as shown in
figure 14b. This reduces the instruction sequence by eight clocks and allows the Read address to be
immediately entered after /CS is asserted low. If the “Continuous Read Mode” bits (M7-0) are any value
other than “Ax” hex, the next instruction (after /CS is raised and then lowered) requires the first byte
instruction code, thus returning to normal operation. A “Continuous Read Mode” Reset instruction can be
used to reset (M7-0) before issuing normal instructions (See 11.2.29 for detailed descriptions).
Instruction (E3h)
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
Byte 1
Byte 2
Byte 3
Byte 4
Figure 14a. Octal Word Read Quad I/O Instruction Sequence (M7-0 = 0xh or NOT Axh)
Publication Release Date: July 08, 2010
- 31 -
Revision E
相关PDF资料
W25Q64CVZEIG IC SPI FLASH 64MBIT 8WSON
W25Q64DWZEIG IC FLASH SPI 64MBIT 8WSON
W25Q64FVSFIG IC SPI FLASH 64MBIT 16SOIC
W25Q80BVSNIG IC SPI FLASH 8MBIT 8SOIC
W25Q80BWSSIG IC FLASH SPI 8MBIT 8SOIC
W25X40BVZPIG IC SPI FLASH 4MBIT 8WSON
W25X64VZEIG IC FLASH 64MBIT 75MHZ 8WSON
W25X80AVDAIZ IC FLASH 16MBIT 100MHZ 8DIP
相关代理商/技术参数
W25Q64BVSFIP 制造商:WINBOND 制造商全称:Winbond 功能描述:64M-BIT SERIAL FLASH MEMORY WITH DUAL AND QUAD SPI
W25Q64BVSSIG 功能描述:SPI FLASH 64MBIT 8-SOIC RoHS:是 类别:集成电路 (IC) >> 存储器 系列:SpiFlash® 标准包装:150 系列:- 格式 - 存储器:EEPROMs - 串行 存储器类型:EEPROM 存储容量:4K (2 x 256 x 8) 速度:400kHz 接口:I²C,2 线串口 电源电压:2.5 V ~ 5.5 V 工作温度:-40°C ~ 85°C 封装/外壳:8-VFDFN 裸露焊盘 供应商设备封装:8-DFN(2x3) 包装:管件 产品目录页面:1445 (CN2011-ZH PDF)
W25Q64BVSSIGTR 制造商:Winbond Electronics Corp 功能描述:SPIFLASH, 64M-BIT, 4KB UNIFORM
W25Q64BVSSIP 制造商:WINBOND 制造商全称:Winbond 功能描述:64M-BIT SERIAL FLASH MEMORY WITH DUAL AND QUAD SPI
W25Q64BVZEIG 功能描述:IC SPI FLASH 64MBIT 8WSON RoHS:是 类别:集成电路 (IC) >> 存储器 系列:SpiFlash® 标准包装:1,000 系列:- 格式 - 存储器:EEPROMs - 串行 存储器类型:EEPROM 存储容量:4K (512 x 8) 速度:400kHz 接口:I²C,2 线串口 电源电压:2.7 V ~ 5.5 V 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC(0.173",4.40mm 宽) 供应商设备封装:8-MFP 包装:带卷 (TR)
W25Q64BVZEIP 制造商:WINBOND 制造商全称:Winbond 功能描述:64M-BIT SERIAL FLASH MEMORY WITH DUAL AND QUAD SPI
W25Q64CV 制造商:WINBOND 制造商全称:Winbond 功能描述:3V 64M-BIT SERIAL FLASH MEMORY WITH DUAL AND QUAD SPI
W25Q64CVDAAG 制造商:WINBOND 制造商全称:Winbond 功能描述:3V 64M-BIT SERIAL FLASH MEMORY WITH DUAL AND QUAD SPI